1. Field of the Invention
The present invention relates to a basic cell and an arrangement structure of the same for use in a SOG (sea of Gates) type large scale integrated circuit (LSI).
2. Prior Art
FIGS. 1 and 2 illustrate the configuration and arrangement structure of a prior art basic cell as disclosed in Japanese Patent Kokai No. 59-44859.
The basic cell 5 is comprised of two P channel MOSFETs formed on an N region 1 and two N channel MOSFETs formed on a P region 3. The P channel MOSFETs include a pair of gate electrodes 2a, 2b symmetrically disposed on the N region 1 in the upper and lower regions with respect to a central line C. The N channel MOSFETs include a pair of gate electrodes 4a, 4b disposed on the P region 3 also symmetrically disposed in the upper and lower regions with respect to the same central line C.
The arrangement structure of the basic cell 5 in the SOG type LSI is as illustrated in FIG. 2. A master slice 6 contains columns of P channel transistors and columns of N channel transistors 8 alternately arranged. The basic cell 5 comprises a combination of the N and P channel MOSFETs of adjacent lines as indicated by a hatched portion in the same figure.
The basic cell structure described above is symmetrical only about the central line C, and hence when the master slice 6 is constructed using the basic cell 5, it is simply allowed to construct the same in a direction where different types of the transistors are disposed, i.e., in the horizontal directions in FIG. 2. It is however impossible to construct the basic cell in a direction where the same type of the transistors is disposed, i.e., in the vertical directions in the same figure. Therefore transistors cannot be used efficiently and hence semiconductor chip real estate is wasted.
For realizing logic cells such as logic gates and logic blocks, etc., on the semiconductor chip, sometimes realization of the same is impossible because of the arrangement structure of the basic cell 5 prevents successful realization. This is caused by the fact that the logic cells can not be constructed in the vertical directions.
Accordingly, high integration of elements in the SOG type LSIs is impractical and the flexibility of a wiring pattern design is limited.